In the construction of an integrated circuit, the designer must compensate for operational difficulties that may arise for the particular construction of the integrated circuit. Typical operational difficulties include excessive current drain, substrate power up, localized heat generation beyond a limit, and other problems that are not apparent in the design of the integrated circuit but that are critical to the operation of the integrated circuit. These operational difficulties, of course, are affected by the physical design of the integrated circuit made from a logical design, the size of the integrated circuit, the process used to construct the integrated circuit, and the manner in which the integrated circuit is operated.
With particular reference to FIG. 1, a typical CMOS transistor 10 may include N-channel transistors 12 and P-channel transistors 14. The transistors 12 and 14 are connected such that they implement particular logic functions or portions of logic functions within an integrated circuit. Each N-channel transistor 12 includes a source 16, a gate 18, and a drain 20 while each P-channel transistor also includes a source 22, a gate 24, and a drain 26.
The N-channel transistor 12 is turned on by applying a voltage exceeding a threshold voltage to the gate 18. Once turned on, the N-channel transistor 12 conducts from its source 16 to its drain 20. Alternatively, the P-channel transistor 14 is turned on by applying a voltage lower than a threshold to its gate 24. Once the transistor is turned on, the P-channel transistor also conducts from its source 22 to its drain 26.
As is shown, when a P-type substrate 30 is used as the base for the integrated circuit, each P-channel transistor 14 is constructed within an N-type well 28 formed in the P-type substrate 30. The use of an N-type well 28 is required to prevent a direct short between the source 22 and substrate. Silicon controlled rectifier ("SCR") latch-up occurs when a forward bias exists at the substrate/well junction. Upon SCR latch-up, the integrated circuit ceases to function properly and consumes large quantities of power. To prevent SCR latch-up between the P-type material of drain 26, the N-type material of the well 28, and the P-type material of the substrate 30, the N-well 28 is tied to a first voltage reference level or V.sub.DD. In this fashion, SCR latch-up is prevented by fixing the potential of the N-type well 28 at the first reference voltage V.sub.DD.
Fixing the well 28 at the first reference voltage V.sub.DD also guarantees that the threshold gate voltage that must be applied to the gate 24 to turn the P-type transistor 14 on will remain constant during operation of the integrated circuit. Because the relative voltage differential between the gate 24 and the N-well 28 determines whether, and how rapidly, the inversion layer between the source 22 and the drain 26 will invert, the voltage differential must be controllable. The application of a voltage to the source 22 or the drain 26 affects the potential of the N-well 28. Thus well ties 32 along the N-type well 28 also serve to fix the voltage of the N-well 28 and ensure that the gate voltage threshold will remain constant. As shown, well ties 32 may be made directly between the source V.sub.DD and the N-well 28 or may be made between the source V.sub.DD and a more highly doped region 36 within the N-well structure.
With the N-channel transistor 12 as well, a voltage applied to the source 16 or drain 20 may alter the voltage of the substrate 30. In such a situation, if the voltage of the substrate 30 is not fixed, the gate threshold voltage required to turn on the N-channel transistor 12 through its application to the gate 18 will vary. Thus, substrate ties 34 are commonly used to fix the voltage potential of the substrate 30 at a reference potential V.sub.SS. As shown, the substrate ties may be made directly to the substrate 30 or may be made to a more highly doped portion of the substrate 35.
The placement of ties within integrated circuits has typically been left up to the circuit designer who generates the physical design of the integrated circuit. Thus, the application of ties has been inconsistent and iterative alterations in their placement between the production of mask sets are sometimes required to enable a correct operation of the integrated circuit. Even when the placement of ties does not cause operational difficulties which must be fixed at a later time, the application or placement of ties within an integrated circuit has been a tedious and difficult process because of the various design rules that influence tie placement. The integrated circuit will have smaller dimensions when the ties are properly placed because properly placed ties allow for more efficient compaction.
The placement of other elements within a physical integrated circuit is also difficult and their improper placement causes operational difficulties within the integrated circuitry. For example, the placement of vias between a first layer and a second layer may interrupt signal paths within both the first layer and the second layer. While the proper placement of a via may increase a highest frequency of operation of the digital circuit, the placement of vias is often left up to the designer and does not include an automated process. Further, in an integrated circuit, antenna diodes are often used to reduce charge induced damage within the integrated circuit. While the antenna diodes reduce charge induced damage, their placement within the integrated circuit is difficult for the same reasons as is the placement of vias. Integrated circuit dimensions will also be reduced upon an efficient placement of vias due to increased compaction efficiencies that are possible.
Thus, there exists a need in the art for a method and apparatus for the automatic placement of ties and connection elements within integrated circuits based upon design rules.